This application claims the priority of Korean Patent Application No. 2001-78181, filed Dec. 11, 2001, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a driving device and method for plasma display panels, and more particularly, to a highly-efficient device and method for driving a plasma display panel, by which the voltage stresses of circuit elements, which constitute the driving device, are significantly reduced, and power consumption and heat emission are accordingly reduced.
2. Description of the Related Art
A plasma display panel (PDP) is a next-generation flat-panel display that displays characters or images using plasma produced by gas discharge. The number of pixels of a PDP, pixels that are two-dimensionally arranged, ranges from several hundreds of thousands to several millions according to the size of a PDP.
FIG. 1 is a circuit diagram of a conventional Webber-type alternating current plasma display panel (AC-PDP) sustaining discharge circuit. In this case, the AC-PDP can be assumed to be a panel capacitance Cp. In FIG. 2, (a)-(j) show the waveforms of switch control signals for switching sequences, the waveform of an output voltage vp at both ends of a plasma display panel obtained based on the switch control signals, and the waveform of current iL, which flows through an inductor Lc. The AC-PDP sustaining discharge circuit can be expressed in the following four modes according to a switching sequence.
In mode 1, immediately before a MOSFET switch Sa1 is turned on, Sx2 is turned on, and both-end voltage vp is maintained 0V. When Sa1 is turned on at t0, mode 1 starts being performed During mode 1, an Lc resonance circuit is formed along a path of Cc1-Sa1-Da-Lc1-C (panel). Accordingly, a resonance current flows through an inductor Lc1, and vp increases. At t1, the current of an inductor on the upper side is 0A, and vp is equal to +Vpk.
In mode 2, at t2, Sa1 is turned off and Sy1 is turned on. At this time, the both-end voltage vp for Sy1 is changed by Vpk, so a switching loss is generated. During mode 2, vp is kept to be+Vs, and the panel maintains a discharge state.
In mode 3, at t3, Sa2 is turned on while Sy1 is turned off. During mode 3, an LC resonance circuit is formed along a path of C-Lc1-Da2-Sa2-Cc1. Accordingly, a resonance current flows through the inductor Lc1, and vp decreases. At t3, the current of an inductor on the lower side is 0A, and vp is decreased to +Vpk.
In mode 4, at t4, Sa2 is turned off, while Sy2 is turned on. At this time, since the both-end voltage vp for Sy2 is +Vpk, a switching loss is generated. During mode 4, vp is maintained to be 0V.
Looking at the voltage stresses of semiconductor devices in the conventional AC-PDP sustaining discharge circuit as described above, a voltage stress of sustaining discharge MOSFET switches Sy1, Sy2, Sx1, and Sx2 is +Vs, a voltage stress of energy recovery MOSFET switches Sa1, Sa2, Sb1, and Sb2 is +Vs/2, and a voltage stress of diodes Da1, Da2, Db1, Db2, Dc1, Dc2, Dc3, and Dc4 is +Vs/2 Considering the fact that a typical PDP operates at a voltage Vs in the range of 160V to 190V, these semiconductor devices are expensive. In addition, parasitic resistance and parasitic capacitance increase, which causes an increase in power loss during switching, and an increase in electromagnetic interference (EMI) and noise in PDP driving circuits.